(1) Field of the Invention
The invention relates to a method of fabricating Semiconductor devices, and more particularly, to the formation of a high performance varactor on silicon in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
A key building block of a CMOS monolithic transceiver is the Phase Locked Loop (PLL) circuit. PLL performance is largely dependent on the characteristics of the voltage-controlled oscillator (VCO). In turn, the monolithic integration of VCO circuits onto silicon-based radio frequency (RF) integrated circuits depends upon the ability to fabricate high quality on-chip varactors. A varactor is defined as a voltage-variable capacitor.
Silicon has been identified as one of the key materials in meeting the demands of wireless communications applications. Silicon-based integrated circuits represent a mature technology with low fabrication costs and high packing density. However, the difficulty of realizing high quality factor (Q) varactors with large tuning ranges remains a great challenge for silicon-based RF integrated circuit design and fabrication.
Most conventional on-chip, or integrated, varactors are implemented as either reverse-biased p-n junctions or as accumulation-mode MOS capacitors. Reverse-biased p-n junction varactors exhibit a limited tuning range for low supply voltages due to technology scaling and reliability issues. Prior art accumulation-mode MOS capacitor varactors exhibit low Q values.
Referring to FIG. 1, a cross-section of a typical MOS varactor is shown. A semiconductor substrate 10 is shown. The semiconductor substrate could comprise either an n-type or a p-type region. A well 17 may be formed in the semiconductor substrate. A drain 15 and a source 16 are formed in the substrate 10 and in the well 17, if used. A thin gate oxide layer 14 is formed overlying the semiconductor substrate 10. A gate electrode 18 is formed overlying the thin gate oxide layer 14. A voltage potential (VG) can be applied to the gate electrode while the drain 15 and the source 16 are connected together to form the other electrode. The drain 15 and the source 16 are commonly called the diffusion.
A prior art MOS varactor comprises a drain 15 and the source 16 of n+ diffusions, an n-well 17, and the p-type substrate 10. The operation of the MOS varactor is described below. The gate 18 and the drain 15 and source 16 contacts are the controlling electrodes. The device capacitance is given by C=C0WL, where W is the gate width, L is the gate length, and C0 is given by:
C0=((1/COX)+(1/COX))xe2x88x921
in which COX and CSi are, respectively, the oxide capacitance and the capacitance of the depletion layer under the gate, per unit area. By applying a positive voltage between the gate 18 and the n-well 17, the surface is accumulated and the device capacitance equals the oxide capacitance, COX. If the applied voltage is reversed, the surface layer is depleted and the series capacitance decreases. The maximum capacitance, per unit area, of the device corresponds to a heavily accumulated surface and equals COX=∈/tOX, where tOX is the thickness of the gate oxide layer. On the other side, the minimum value (Cdmin) is reached when the voltage difference between the electrode equals the threshold voltage. Beyond this point, an inversion layer is formed under the gate. At low frequency, this effect brings the value of the device capacitance close to the oxide capacitance. At high frequency, where the varactor is typically operated, this effect is not seen and the capacitance remains at its minimum value.
Referring now to FIG. 2, a top view of a prior art MOS varactor is shown. Here, the gate electrode 18 is shown intersecting a section of the diffusion 15 and 16. The varactor is formed by the intersection. This varactor forms a one-dimensional cell where the drain and source sides of the capacitor go in a single direction.
Referring now to FIG. 3, an equivalent circuit model of the prior art varactor in the accumulation mode is shown. The varactor is modeled as a series of passive components connected in a network. The gate electrode is modeled as a series inductance (Ls) 50, a gate resistance (Rg) 52, a gate oxide capacitance (Cox) 54, and a semiconductor capacitance (Csi) 56. The substrate is modeled as a well capacitance (Cw) 68 and a well resistance (Rw) 66. The drain and source regions are each modeled as a first dimension accumulation layer resistance (Racc(1)) 60 and 62 and a first dimension lightly doped drain (LDD) and contact resistance (Rd(1)) 58 and 64. The drain and source and the substrate are grounded 72 while the variable voltage is applied to the gate 70.
Referring now to FIG. 4, an equivalent circuit model of the prior art varactor in the depletion mode is shown. The gate is again modeled as a series inductance (Ls) 50, a gate resistance (Rg) 52, and a gate oxide capacitance (Cox) 54. In depletion, however, the semiconductor capacitance (Csi) 56 is attached to the substrate rather than the gate. The substrate is also modeled as a well capacitance (Cw) 68 and a well resistance (Rw) 66. The drain and source regions are each modeled as a first dimension lightly doped drain (LDD) and contact resistance (Rd(1)) 58 and 64 and a first dimension channel-to-S/D depletion capacitance (Cd(1)) 74 and 76.
The changes in the equivalent circuit model of the varactor from the accumulation mode (FIG. 3) to the depletion mode (FIG. 4) reflect the presence of the depletion region underlying the gate oxide layer 14 during depletion mode. The effective series resistance of the prior art MOS varactor in accumulation mode is given by:
Rsxe2x89xa1Racc(1)/2.
The effective series resistance in depletion mode is given by:
Rsxe2x89xa1Rw(Csi/(Csi+2Cd(1)))2.
The effective series capacitance in the accumulation mode is given by:
Cs=CoxCsi/(Cox+Csi).
Finally, the effective series capacitance in the depletion mode is given by:
Cs=(Cox(Csi+2Cd(1)))/(Cox+Csi+2Cd(1)).
Several prior art approaches disclose methods to form on-chip varactors in the manufacture of an integrated circuit device. U.S. Pat. No. 5,405,790 to Rahim et al discloses a p-n junction varactor fabricated in a BiCMOS process. U.S. Pat. No. 5,173,835 to Cornett et al teaches a metal-insulator-silicon (MIS) varactor. A metal oxide, such as zirconium titanate, is used for the dielectric insulator. A high resistivity layer is used underlying the insulator to support large depletion regions under negative bias. U.S. Pat. No. 4,170,818 to Tobey, Jr. et al discloses a method to form a voltage reference circuit based on differences in the gate-to-channel barriers between two JFET devices. U.S. Pat. No. 5,854,117 to Huisman et al teaches a method to form a varicap diode p-n junction for use as a varactor. U.S. Pat. No. 4,226,648 to Goodwin et al discloses a method to form a hyper-abrupt varactor diode p-n junction. A. S. Poret et al, xe2x80x9cDesign of High-Q Varactors for Low-Power Wireless Application using a Standard CMOS Process,xe2x80x9d IEEE 1999 Custom Integrated Circuits Conference, teaches a varactor. R. Castello et al, xe2x80x9cA +/xe2x88x9230% Tuning Range Varactor Compatible with Future Scaled Technologies,xe2x80x9d 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp.34-35, June 1998, teaches a varactor. W. Wong et al, xe2x80x9cWide Tuning Range Inversion-Mode Gated Varactor and Its Application on a 2-GHz VCO,xe2x80x9d 1999 Symposium on VLSI Circuits Digest of Technical Papers, teaches a varactor. F. Svelto et al, xe2x80x9cA Metal-Oxide-Semiconductor Varactor,xe2x80x9d IEEE Electron Device Letters vol. 20, no.4, pp.164-166, 1999, teaches a varactor. J. N. Burghartz et al, xe2x80x9cIntegrated RF Components in a SiGe Bipolar Technology,xe2x80x9d IEEE J. Solid State Circuits, vol.32, no.9, pp.1440-1445, 1997, teaches a varactor. T. Soorapanth et al, xe2x80x9cAnalysis and Optimization of Accumulation-Mode Varactor for RF Ics,xe2x80x9d 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp.32-33, June 1998, teaches a varactor. C. M. Hung et al, xe2x80x9cHigh-Q Capacitors Implemented in a CMOS Process for Low-Power Wireless Applications,xe2x80x9d IEEE Tran. Microwave Theory Tech, vol.46, pp.505-510, May 1998, teaches a varactor.
A principal object of the present invention is to provide an improved varactor device for use in an integrated circuit device.
A further object of the present invention is to provide an improved varactor device that is integrated in a standard MOS process.
A yet further object of the present invention is to improve the Q-value of a varactor device by using a two-dimensional array layout technique.
Another yet further object of the present invention is to reduce the effective resistance of the varactor device by using a two-dimensional array layout technique.
Another further object of the present invention is to provide an effective and very manufacturable method of fabricating an improved varactor device in the manufacture of an integrated circuit.
In accordance with the objects of this invention, a new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.
Also in accordance with the objects of this invention, a new method of fabricating a MOS varactor device has been achieved. A semiconductor substrate of either n-type or p-type is provided. A well of either n-type or p-type may be formed in the semiconductor substrate. A dielectric layer is formed overlying the semiconductor substrate. A top electrode layer, preferably of polysilicon, is deposited overlying the dielectric layer. The top electrode layer is patterned to form a single polygon containing a two-dimensional array of openings therein. Ions are implanted into the semiconductor substrate through the two-dimensional array of openings to form diffusion junctions of either n-type or p-type. The diffusion junctions are thereby formed as a two-dimensional array. An interlevel dielectric layer is deposited overlying the polysilicon layer and the diffusion junctions. The interlevel dielectric layer is patterned to form a two-dimensional array of contact openings to the underlying diffusion junctions. A metal layer is deposited overlying the dielectric layer and filling the contact openings. The metal layer is patterned to complete the manufacture of the integrated circuit device.